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authorSubrata Banik <subrata.banik@intel.com>2019-04-11 16:34:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-04-17 15:05:08 +0000
commit0a9be33a8aa8e41663c58e0f2f1641f44c7cf5de (patch)
tree93e9081bee530feb4b7801f10682fb0dcaa9f257 /src/soc/intel/common/block
parent26c43b7a77bdf28680ef663ef6eb61f6bf8252ab (diff)
soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency. As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H This patch also adds header file to capture Intel processor model number. BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor 2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC Method 2 actually reduce ~25ms of boot performance time. Note: Method 2 is recommended from gen 6 processor onwards. Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/timer/timer.c64
1 files changed, 61 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c
index 12988856e4..e60ac4d26d 100644
--- a/src/soc/intel/common/block/timer/timer.c
+++ b/src/soc/intel/common/block/timer/timer.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,12 +13,70 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
+#include <arch/intel-family.h>
+#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <intelblocks/msr.h>
+static int get_processor_model(void)
+{
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, cpuid_eax(1));
+
+ return c.x86_model;
+}
+
+/*
+ * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX
+ *
+ * Time Stamp Counter
+ * CPUID Initial EAX value = 0x15
+ * EAX Bit 31-0 : An unsigned integer which is the denominator of the
+ * TSC/"core crystal clock" ratio
+ * EBX Bit 31-0 : An unsigned integer which is the numerator of the
+ * TSC/"core crystal clock" ratio
+ * ECX Bit 31-0 : An unsigned integer which is the nominal frequency of the
+ * core crystal clock in Hz.
+ * EDX Bit 31-0 : Reserved = 0
+ *
+ * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3
+ */
unsigned long tsc_freq_mhz(void)
{
- msr_t msr = rdmsr(MSR_PLATFORM_INFO);
- return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff));
+ unsigned int core_crystal_nominal_freq_khz;
+ struct cpuid_result cpuidr;
+
+ /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
+ cpuidr = cpuid(0x15);
+
+ if (!cpuidr.ebx || !cpuidr.eax)
+ return 0;
+
+ core_crystal_nominal_freq_khz = cpuidr.ecx / 1000;
+
+ if (!core_crystal_nominal_freq_khz) {
+ switch (get_processor_model()) {
+ case CPU_MODEL_INTEL_SKYLAKE_MOBILE:
+ case CPU_MODEL_INTEL_SKYLAKE_DESKTOP:
+ case CPU_MODEL_INTEL_KABYLAKE_MOBILE:
+ case CPU_MODEL_INTEL_KABYLAKE_DESKTOP:
+ case CPU_MODEL_INTEL_CANNONLAKE_MOBILE:
+ case CPU_MODEL_INTEL_ICELAKE_MOBILE:
+ core_crystal_nominal_freq_khz = 24000;
+ break;
+ case CPU_MODEL_INTEL_ATOM_DENVERTON:
+ core_crystal_nominal_freq_khz = 25000;
+ break;
+ case CPU_MODEL_INTEL_ATOM_GOLDMONT:
+ case CPU_MODEL_INTEL_ATOM_GEMINI_LAKE:
+ core_crystal_nominal_freq_khz = 19200;
+ break;
+ }
+ }
+
+ return (core_crystal_nominal_freq_khz * cpuidr.ebx / cpuidr.eax) /
+ 1000;
}