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authorMartin Roth <martin@coreboot.org>2021-10-01 14:53:22 -0600
committerMartin Roth <martinroth@google.com>2021-10-05 18:07:08 +0000
commit26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch)
tree8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/intel/common/block/usb4/Kconfig
parent50863daef8ed75c0cb3dfd375e7622c898de5821 (diff)
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/usb4/Kconfig')
-rw-r--r--src/soc/intel/common/block/usb4/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig
index d4e1c25aa1..bc1eb19d49 100644
--- a/src/soc/intel/common/block/usb4/Kconfig
+++ b/src/soc/intel/common/block/usb4/Kconfig
@@ -25,4 +25,4 @@ config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
depends on SOC_INTEL_COMMON_BLOCK_USB4
select PCIEXP_HOTPLUG
help
- Enable USB4 PCIe resources for reserving hotplug busses and memory.
+ Enable USB4 PCIe resources for reserving hotplug buses and memory.