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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:42:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:35:06 +0000 |
| commit | b887adf7a56f2877c41e808002f30841a6679eb6 (patch) | |
| tree | 21610d86c82b79f9c72e89b4be09fac4035d2505 /src/soc/intel/common/block/timer | |
| parent | 3e42ee05d86c1de3ed23dddf08fd8e6451bdea92 (diff) | |
soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/timer')
0 files changed, 0 insertions, 0 deletions