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authorJeremy Soller <jeremy@system76.com>2020-12-29 11:18:01 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-01-11 07:39:54 +0000
commitb1fa231d76a5bb41a61a1c2907ab27e8ef9999bb (patch)
treee30adaa890981e5558b6bcfe773a2448fc3ac56a /src/soc/intel/common/block/timer/timer.c
parent3ba2c1a63e86a7887dad74a06c11145a619a194b (diff)
soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL), and oryp6 (CML). References: - TigerLake FSP Integration Guide - Intel Document Number 337868-002 Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49104 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/timer/timer.c')
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