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author | Zheng Bao <fishbaozi@gmail.com> | 2024-03-15 13:46:51 +0800 |
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committer | Martin L Roth <gaumless@gmail.com> | 2024-03-17 16:56:43 +0000 |
commit | 07e050804f8cd1758302a1a8ae001b26315737e5 (patch) | |
tree | d02a5df9fa90a27e0d9b272ddd39289272f49d42 /src/soc/intel/common/block/thermal | |
parent | caa50f30b7779c1aeb315ddf5738966bc278e9a8 (diff) |
amdfwtool: Set the table size only for FWs
The entry in the table has two categaries, file and pointer. For the
pointer, it does not take table space. The ISH, PSP level 2, BIOS
table are all the pointer type. So integration function only packs FWs
located in folder amd_blobs. And only FWs increase the table size.
So the table size is only set once. Later calls only update the count
and fletcher. The table has a header at least, so the size can not be
0.
The fill_dir_header can take the parameter count as 0, such PSP level
1 only with ISH-A and ISH-B. It doesn't have any file type entries.
This actually reverts
https://review.coreboot.org/c/coreboot/+/78274
and adds other changes.
TEST=Identical test on all AMD SOC platform
Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/thermal')
0 files changed, 0 insertions, 0 deletions