diff options
| author | John <john.zhao@intel.com> | 2022-03-09 17:51:56 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 16:19:18 +0000 |
| commit | 848b42558c29aca8e08564303f9a3ab8007722ac (patch) | |
| tree | 51757aabc8ebddd194ec1f18807907f315751fe4 /src/soc/intel/common/block/tcss | |
| parent | 740eee5eec2a978192e8b74327cb96b735b7d0ed (diff) | |
soc/intel/common: Abstract the common TCSS functions
This change abstracts the common TCSS functions for pad configuration
and Thunderbolt authentication.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block/tcss')
| -rw-r--r-- | src/soc/intel/common/block/tcss/Kconfig | 13 | ||||
| -rw-r--r-- | src/soc/intel/common/block/tcss/tcss.c | 25 |
2 files changed, 5 insertions, 33 deletions
diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 0b80cb951f..2e679138cd 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -9,16 +9,3 @@ config ENABLE_TCSS_DISPLAY_DETECTION depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP help Enable displays to be detected over Type-C ports during boot. - -config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR - def_bool n - depends on SOC_INTEL_COMMON_BLOCK_TCSS - help - Enable TCSS registers access through REGBAR for platforms like - Tiger Lake and Alder Lake - -config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI - def_bool n - depends on SOC_INTEL_COMMON_BLOCK_TCSS - help - Enable TCSS registers access through Sideband interface on applicable SoC platforms diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index e0ca90d7e8..f1a3584400 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -355,7 +355,7 @@ static uint32_t calc_bias_ctrl_reg_value(gpio_t pad) cpu_pid; } -static void tcss_configure_aux_bias_pads_regbar( +void tcss_configure_aux_bias_pads_regbar( const struct typec_aux_bias_pads *pads) { for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -368,16 +368,6 @@ static void tcss_configure_aux_bias_pads_regbar( } } -static void tcss_configure_aux_bias_pads( - const struct typec_aux_bias_pads *pads) -{ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR)) - tcss_configure_aux_bias_pads_regbar(pads); - else - printk(BIOS_ERR, "%s: Error: No TCSS configuration method is selected!\n", - __func__); -} - const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) { static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; @@ -423,19 +413,14 @@ void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PO tcss_init_mux(i, &port_map[i]); /* This should be performed before alternate modes are entered */ - tcss_configure_aux_bias_pads(aux_bias_pads); + if (tcss_ops.configure_aux_bias_pads) + tcss_ops.configure_aux_bias_pads(aux_bias_pads); if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) tcss_configure_dp_mode(port_map, num_ports); } -uint32_t tcss_valid_tbt_auth(void) +bool tcss_valid_tbt_auth(void) { - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR)) { - return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; - } else { - printk(BIOS_ERR, "%s: Error: No validation for Thunderbolt authentication!\n", - __func__); - return 0; - } + return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; } |