diff options
| author | Rex Chou <rex_chou@compal.corp-partner.google.com> | 2023-08-04 15:29:59 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:03:11 +0000 |
| commit | 684eca7dd2187346405180425d3537ed48db3c47 (patch) | |
| tree | 1db81029a650089496e5edd6bb901ea97b84f366 /src/soc/intel/common/block/spi/spi.c | |
| parent | 8c77e58cd6a8caaf0c75916391d04e43e1a11aa9 (diff) | |
mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/spi/spi.c')
0 files changed, 0 insertions, 0 deletions