diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-06 15:20:19 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-02-07 08:09:12 +0000 |
| commit | 828c39eb6ba4aa72ffb027a0fc70d8ec78a83d24 (patch) | |
| tree | 6acb3bc4c3d06e83a92650c33c84017633f48285 /src/soc/intel/common/block/sata/Kconfig | |
| parent | 9076b7bd077810cb219ef2a58e999fad2b3e0b93 (diff) | |
soc/intel/common/block: Fix SATA chipset register definitions anomalies
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.
Add new Kconfig option to address this delta between different PCH.
Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/sata/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/sata/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig index 6b24f595c4..98ff6967c9 100644 --- a/src/soc/intel/common/block/sata/Kconfig +++ b/src/soc/intel/common/block/sata/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SATA bool help Intel Processor common SATA support + +config SOC_AHCI_PORT_IMPLEMENTED_INVERT + depends on SOC_INTEL_COMMON_BLOCK_SATA + bool + help + SATA PCI configuration space offset 0x92 Port + implement register bit 0-2 represents respective + SATA port enable status as in 0 = Disable; 1 = Enable. + If this option is selected then port enable status will be + inverted as in 0 = Enable; 1 = Disable. |