From 828c39eb6ba4aa72ffb027a0fc70d8ec78a83d24 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 6 Feb 2018 15:20:19 +0530 Subject: soc/intel/common/block: Fix SATA chipset register definitions anomalies SATA PCH configuration space registers bit mapping is different for various SOCs hence common API between SPT-PCH and CNL-PCH causing issue. Add new Kconfig option to address this delta between different PCH. Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/23589 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/sata/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/common/block/sata/Kconfig') diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig index 6b24f595c4..98ff6967c9 100644 --- a/src/soc/intel/common/block/sata/Kconfig +++ b/src/soc/intel/common/block/sata/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SATA bool help Intel Processor common SATA support + +config SOC_AHCI_PORT_IMPLEMENTED_INVERT + depends on SOC_INTEL_COMMON_BLOCK_SATA + bool + help + SATA PCI configuration space offset 0x92 Port + implement register bit 0-2 represents respective + SATA port enable status as in 0 = Disable; 1 = Enable. + If this option is selected then port enable status will be + inverted as in 0 = Enable; 1 = Disable. -- cgit v1.2.3