diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/common/block/pmc | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/pmc')
| -rw-r--r-- | src/soc/intel/common/block/pmc/pmc.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pmc/pmclib.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1f25d756f3..43543a1cc5 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -66,7 +66,7 @@ static void pch_pmc_add_io_resources(struct device *dev, cfg->abase_addr, cfg->abase_size, IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); - if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) { + if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) { /* * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've * observed cases where the BAR reads back as 0, but the IO @@ -105,7 +105,7 @@ static void pch_pmc_read_resources(struct device *dev) void pmc_set_acpi_mode(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 6c967adfb0..f58d36246e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -384,7 +384,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -432,7 +432,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps) return ps->prev_sleep_state; } -#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK) +#if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. |