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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-16 15:07:15 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-07 19:59:29 +0000 |
| commit | f94405219c93613471a33db9a76bb6106469eb1b (patch) | |
| tree | 7ded07db717e532a726f3d4499c68a759f6ed403 /src/soc/intel/common/block/pcie | |
| parent | ef5f7ee696097174f9d1f01e9b04ea8f1354cfe0 (diff) | |
soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
0 files changed, 0 insertions, 0 deletions