diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-12-28 13:49:28 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-12 08:00:33 +0000 |
| commit | d64d426b4fb0730ed149571334331616582b3e00 (patch) | |
| tree | 0600be57c1cfbb39fb6fa476ed34cca76d7a3476 /src/soc/intel/common/block/pcie | |
| parent | 28e61f16341f2a2715ee8e963038f42e6e799eba (diff) | |
soc/intel/common/pcie: Add helper function for getting mask of enabled ports
This change adds a helper function `pcie_rp_enable_mask()` that
returns a 32-bit mask indicating the status (enabled/disabled) of PCIe
root ports (in the groups table) as configured by the mainboard in the
device tree.
With this helper function, SoC chip config does not need to add
another `PcieRpEnable[]` config to identify what root ports are
enabled.
Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie_helpers.c | 40 |
2 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index e2ad685bc3..521ca6b37e 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,4 +1,7 @@ subdirs-y += ./* +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c new file mode 100644 index 0000000000..31451d07f6 --- /dev/null +++ b/src/soc/intel/common/block/pcie/pcie_helpers.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <intelblocks/pcie_rp.h> +#include <stdint.h> + +static uint32_t pcie_slot_enable_mask(unsigned int slot, unsigned int count) +{ + uint32_t mask = 0; + unsigned int i; + const struct device *dev; + + for (i = 0; i < count; i++) { + dev = pcidev_on_root(slot, i); + if (is_dev_enabled(dev)) + mask |= BIT(i); + } + + return mask; +} + +uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups) +{ + uint32_t mask = 0; + uint32_t offset = 0; + const struct pcie_rp_group *group; + + for (group = groups; group->count; ++group) { + if (group->count + offset >= sizeof(mask) * 8) { + printk(BIOS_ERR, "ERROR: %s: Root port count greater than mask size!\n", + __func__); + break; + } + mask |= pcie_slot_enable_mask(group->slot, group->count) << offset; + offset += group->count; + } + + return mask; +} |