diff options
| author | John Zhao <john.zhao@intel.com> | 2020-12-15 14:36:51 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-11 07:36:52 +0000 |
| commit | 3ba2c1a63e86a7887dad74a06c11145a619a194b (patch) | |
| tree | 694af01a32981aa012bf42ff36121dc0756080ab /src/soc/intel/common/block/pcie | |
| parent | c1befbe5d079b24316a69ce3c0d82b0e5b8d88ce (diff) | |
mb/google/volteer: Set FORCE_PWR low at boot time
While FORCE_PWR is set high, it prevents retimer from entering low power
state. S0ix failure occurs while USB4 Gatkex is connected on Port-0.
This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be
toggled by kernel through DSM method while updating retimer firmware.
BUG=b:174166586
Cq-Depend: chromium:2594438
TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
0 files changed, 0 insertions, 0 deletions