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authorAngel Pons <th3fanbus@gmail.com>2021-01-06 00:48:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-13 12:13:45 +0000
commit2fa7f07fada00eb031360797a689e38551802114 (patch)
tree20713f3213037dc58e9158e8eacb2c9f0b28b466 /src/soc/intel/common/block/lpss/Kconfig
parent50a80b3d08306958bf0151223ac70bee471fed56 (diff)
sb/intel/bd82x6x: Correct xHCI sleep workaround
The S3/S4 workaround is specific to Panther Point stepping A0, and it is wrongly implemented. Rewrite the whole function as per reference code. Since this runs in SMM, be overly cautious and double-check everything. Do not rely on GNVS to determine if xHCI is enabled. Instead, check whether the corresponding bit in the Function Disable register is set. Only Panther Point has xHCI, so exit early if this is not the case. Change-Id: Iabce6c52fac781dc694f5b589fab2e9fe438f3f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/lpss/Kconfig')
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