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authorMichael Niewöhner <foss@mniewoehner.de>2021-01-17 01:42:15 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-20 18:29:06 +0000
commit71624cd94f85b8cdad7ae59e9af6a9a509ba51c3 (patch)
treea081ab3a7a6423b9caba8df89ed061d8e0ab1e37 /src/soc/intel/common/block/lpc
parent2cbe3df2cd8f827c0ef67c5e8fd0688dd0aee103 (diff)
soc/intel/*: drop broken LPC mmio code
The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/block/lpc')
-rw-r--r--src/soc/intel/common/block/lpc/lpc.c8
-rw-r--r--src/soc/intel/common/block/lpc/lpc_lib.c22
2 files changed, 0 insertions, 30 deletions
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index e754237ffa..0bffaf62e6 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -59,14 +59,6 @@ static void pch_lpc_loop_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_IO)
lpc_open_pmio_window(res->base, res->size);
-
- if (res->flags & IORESOURCE_MEM) {
- /* Check if this is already decoded. */
- if (lpc_fits_fixed_mmio_window(res->base, res->size))
- continue;
-
- lpc_open_mmio_window(res->base, res->size);
- }
}
pch_lpc_set_child_resources(dev);
}
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index d050ee36e5..6c300a2d52 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -148,28 +148,6 @@ void lpc_open_mmio_window(uintptr_t base, size_t size)
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
}
-bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
-{
- resource_t res_end, range_end;
- const struct lpc_mmio_range *range;
- const struct lpc_mmio_range *lpc_fixed_mmio_ranges =
- soc_get_fixed_mmio_ranges();
-
- for (range = lpc_fixed_mmio_ranges; range->size; range++) {
- range_end = range->base + range->size;
- res_end = base + size;
-
- if ((base >= range->base) && (res_end <= range_end)) {
- printk(BIOS_DEBUG,
- "Resource %lx size %zx fits in fixed window"
- " %lx size %zx\n",
- base, size, range->base, range->size);
- return true;
- }
- }
- return false;
-}
-
/*
* Set FAST_SPIBAR BIOS Control register based on input bit field.
*/