diff options
| author | Ethan Tsao <ethan.tsao@intel.com> | 2021-10-13 12:37:05 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-27 22:17:41 +0000 |
| commit | eaf71b0778fb928850d6cb1323994e7cc35e3278 (patch) | |
| tree | 24e517148efd2990f4deb145c92e8bc77cd9ada1 /src/soc/intel/common/block/include | |
| parent | a1b299cd6933f3c9c6b2d74e1f044d858f96fcda (diff) | |
soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement
Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC.
Reference:
https://github.com/otcshare/CCG-ADL-Generic-Full
ClientOneSiliconPkg\Include\Register\PmcRegs.h
#define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2
It is consumed in below.
ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c
Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pmc_ipc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index 1877fe43fb..485833d8c4 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -40,6 +40,7 @@ /* IPC command for reading PMC registers */ #define PMC_IPC_CMD_RD_PMC_REG 0xA0 +#define PMC_IPC_CMD_SUBCMD_RD_PMC_REG 0x02 /* IPC command to enable/disable PCIe SRCCLK */ #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC |