soc/intel/common/block/gpio: Add `gpio_lock_pad()`

This commit adds a method for locking a GPIO pad configuration and its
TX state.  When the configuration is locked, the following registers
become Read-Only and software writes to these registers have no effect.

  Pad Configuration registers
  GPI_NMI_EN
  GPI_SMI_EN
  GPI_GPE_EN

Note that this is only effective if the pad is owned by the host (set in
the PAD_OWN register).

Intel platforms that wish to leverage this function need to define the
PADCFGLOCK offset for their platform.

BUG=b:191189275
BRANCH=None
TEST=With some other code, call gpio_lock_pad() against a pad and verify
that the pad configuration is locked and the state of the pad cannot be
changed from the OS.

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Id3c0da2f6942099c0289ca1e33a33c176f49d380
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

1 files changed, 33 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 86a36d5e6b..8496db32c5 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -121,6 +121,7 @@ struct pad_community {
 	uint16_t	gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */
 	uint16_t	gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */
 	uint16_t	pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */
+	uint16_t	pad_cfg_lock_offset; /* offset to first PADCFGLOCK Reg */
 	uint8_t		gpi_status_offset;  /* specifies offset in struct
 						gpi_status */
 	uint8_t		port;	/* PCR Port ID */
@@ -197,6 +198,38 @@ void gpio_configure_pads_with_override(const struct pad_config *base_cfg,
  */
 void *gpio_dwx_address(const gpio_t pad);
 
+enum gpio_lock_action {
+	GPIO_LOCK_CONFIG = 0x1,
+	GPIO_LOCK_TX	 = 0x2,
+	GPIO_LOCK_FULL	 = GPIO_LOCK_CONFIG | GPIO_LOCK_TX,
+};
+
+/*
+ * Lock a GPIO's configuration.
+ *
+ * The caller may specify if they wish to only lock the pad configuration, only
+ * the TX state, or both.  When the configuration is locked, the following
+ * registers become Read-Only and software writes to these registers have no
+ * effect.
+ *
+ *	Pad Configuration registers,
+ *	GPI_NMI_EN,
+ *	GPI_SMI_EN,
+ *	GPI_GPE_EN
+ *
+ * Note that this is only effective if the pad is owned by the host and this
+ * function may only be called in SMM.
+ *
+ * @param pad: GPIO pad number
+ * @param action: Which register to lock.
+ * @return 0 if successful,
+ * 1 - unsuccessful
+ * 2 - powered down
+ * 3 - multi-cast mixed
+ * -1 - sideband message failed or other error
+ */
+int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action);
+
 /*
  * Returns the pmc_gpe to gpio_gpe mapping table
  *