diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-18 13:43:19 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-05-28 23:54:08 +0000 |
| commit | c7854b064f7d245f8f25c95f8775c0cfd66f086f (patch) | |
| tree | c2adddfe0573ed4b988dab623c0791896bcd0ab0 /src/soc/intel/common/block/include | |
| parent | 90e683b3071030c7f0f56b6bd52dc3bb0d3d9578 (diff) | |
soc/intel/tigerlake: Implement soc_get_pmc_mux_device()
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later
patch), and it needs to get access to the PMC.MUX device so that its
ACPI path can be retrieved. This provides a weak function to return NULL
for all Intel SoCs except for Tiger Lake, which locates the device if it
is found in the devicetree.
Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pmc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 329bbe9bd7..75e212740d 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -51,4 +51,13 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg); /* API to set ACPI mode */ void pmc_set_acpi_mode(void); +/* + * Returns a reference to the PMC MUX device for the given port number. + * Returns NULL if not found or SoC does not support PMC MUX. + * + * Input: Port number (0-based) + * Output: Const pointer to PMC MUX device + */ +const struct device *soc_get_pmc_mux_device(int port_number); + #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ |