diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-11-20 17:56:44 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-23 03:48:32 +0000 |
| commit | 8c974509ea90eec18e22027c3e71de3e875fc964 (patch) | |
| tree | 63e4a193eaedede47dab4fd50c234fbfd79312f4 /src/soc/intel/common/block/include | |
| parent | d05ea79e40c4a7c6e19a3804ad14eaa4ece38402 (diff) | |
soc/intel/common: Define post codes
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/post_codes.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h new file mode 100644 index 0000000000..d7c0ef1cfa --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_POST_CODES_H +#define SOC_INTEL_COMMON_BLOCK_POST_CODES_H + +/* common/block/cpu/car/cache_as_ram.s */ +#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 +#define POST_SOC_NO_RESET 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 +#define POST_SOC_CLEAR_VAR_MTRRS 0x23 +#define POST_SOC_SET_UP_CAR_MTRRS 0x24 +#define POST_SOC_BOOTGUARD_SETUP 0x25 +#define POST_SOC_CLEARING_CAR 0x26 +#define POST_SOC_DISABLE_CACHE_EVICT 0x27 +#define POST_SOC_CAR_NEM_ENHANCED 0x28 +#define POST_SOC_CAR_INIT_DONE 0x29 +#define POST_SOC_BEFORE_CARSTAGE 0x2a + +/* common/block/cpu/car/cache_as_ram_fsp.S */ +#define POST_BOOTBLOCK_CAR 0x21 + +/* common/block/cse/cse.c */ +#define POST_CODE_ZERO 0x00 +#endif |