diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 19:09:34 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-02-23 08:53:38 +0000 |
| commit | 829e8e65b93963d15367092cd3d364c230465720 (patch) | |
| tree | ebcee8a625ed81f6beffe9a0324c713d6a20b9a6 /src/soc/intel/common/block/include | |
| parent | 6b2b8355b321301f39335246afc0db71496961c3 (diff) | |
soc/intel: Use common codeflow for MP init
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*:
Remove lapic from devicetree).
Alderlake cpu code was linked in romstage but unused so drop it.
Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 9029c91c45..f7cdf87334 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -24,16 +24,6 @@ int get_cpu_count(void); void get_microcode_info(const void **microcode, int *parallel); /* - * Perform BSP and AP initialization - * This function can be called in below cases - * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude - * this call if user has selected USE_INTEL_FSP_MP_INIT) - * 2. coreboot would like to take APs control back after FSP-S has done with MP - * initialization based on user select USE_INTEL_FSP_MP_INIT - */ -void init_cpus(void); - -/* * This function will perform any recommended CPU (BSP and AP) initialization * after coreboot has done the multiprocessor initialization (before FSP-S) * and prior to coreboot perform post_cpus_init (after DRAM resources are set). @@ -52,14 +42,4 @@ void before_post_cpus_init(void); */ void soc_core_init(struct device *dev); -/* - * In this function SOC must fill required mp_ops params, also it - * should call these mp_ops callback functions by calling - * mp_init_with_smm() function from x86/mp_init.c file. - * - * Also, if there is any other SOC specific functionalities to be - * implemented before or after MP Init, it can be done here. - */ -void soc_init_cpus(struct bus *cpu_bus); - #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */ |