diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-01 07:56:40 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:50:29 +0000 |
| commit | 801dbf4f09db70801ece813dad7fec3129759ef1 (patch) | |
| tree | 44dbbf6852ddd6dd5bd2d29877f256d87c4f94f9 /src/soc/intel/common/block/include | |
| parent | 644502311571cf315fd2cdeb080a14f87d0b9e7c (diff) | |
soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
This patch implements heci_init() API that perform initialization of
all HECI devices as per MAX_HECI_DEVICES config.
BUG=none
TEST=Able to build and boot google/taeko with this change. No CSE
error observed with `heci_init()` called from romstage.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 28bc2503be..322e9f3d02 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -333,6 +333,9 @@ struct cse_boot_perf_rsp { */ void cse_init(uintptr_t bar); +/* Initialize the HECI devices. */ +void heci_init(void); + /* * Send message from BIOS_HOST_ADDR to cse_addr. * Sends snd_msg of size snd_sz, and reads message into buffer pointed by |