diff options
author | Subrata Banik <subrata.banik@intel.com> | 2018-05-17 18:40:32 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-10 12:18:34 +0000 |
commit | 7bc4dc5648c6ff37a847e99d7acee11e3e72a79d (patch) | |
tree | c7137be28a68c96d3711c77ef7bbd9d288d6569f /src/soc/intel/common/block/include | |
parent | e7184b0ad07b0d3fe3e2f58bacd5e10e3cd88a79 (diff) |
soc/intel/common/block: Move tco common functions into block/smbus
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.
BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.
Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pmclib.h | 7 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/tco.h | 36 |
2 files changed, 36 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index e1c29be1ad..82eb2ae4c4 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -93,13 +93,6 @@ uint32_t pmc_clear_tco_status(void); */ const char *const *soc_tco_sts_array(size_t *a); -/* - * Resets the tco status registers. This function clears the tco_sts register - * and returns the sts and enable bits set. - */ -uint32_t soc_reset_tco_status(void); - - /* GPE */ /* diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h new file mode 100644 index 0000000000..86fa33b61a --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_TCO_H +#define SOC_INTEL_COMMON_BLOCK_TCO_H + +#include <stdint.h> + +/* + * Enable TCO BAR using SMBUS TCO base to access TCO related register + * also disable the timer. + */ +void tco_configure(void); +/* Lockdown TCO registers before booting to OS */ +void tco_lockdown(void); +/* + * Resets the tco status registers. This function clears the tco_sts register + * and returns the status bits set. + */ +uint32_t tco_reset_status(void); +uint16_t tco_read_reg(uint16_t tco_reg); +void tco_write_reg(uint16_t tco_reg, uint16_t value); + +#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ |