summaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block/include
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2020-08-05 21:36:11 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-04-22 19:41:29 +0000
commit6e64c1a4e09de71d359c3123f7be1dfceba1f0a1 (patch)
tree0e53221b6d5a9da8dee9224a6b8b6b27d546a62b /src/soc/intel/common/block/include
parent70299d916891b718606cad151cf56b1d410cf96a (diff)
soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per thread
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it once. Tested on Acer ES1-572 by checking chipsec results. Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 6fc31b374e..7e3deb0fd4 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -151,7 +151,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
void mca_configure(void);
/* Lock chipset memory registers to protect SMM */
-void cpu_lt_lock_memory(void *unused);
+void cpu_lt_lock_memory(void);
/* Get a supported PRMRR size in bytes with respect to users choice */
int get_valid_prmrr_size(void);