diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-22 21:56:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-31 10:35:52 +0000 |
| commit | 5ce66da1b5ad873cbaa694c850f8816074837e02 (patch) | |
| tree | f3b9040dad2695186102683f4f42b5fc6915c0dd /src/soc/intel/common/block/include | |
| parent | af1cbe2278b4ca3252d48ba36814db940e9d4237 (diff) | |
soc/intel/common: add common function to set LT_LOCK_MEMORY
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which
locks most of the chipset BAR registers in accordance to Intel BWG.
Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 8630fd1eb5..1aa88e156d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void); /* Configure Machine Check Architecture support */ void mca_configure(void); +/* Lock chipset memory registers to protect SMM */ +void cpu_lt_lock_memory(void *unused); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e202..3e67fd779d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -67,6 +67,8 @@ #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 +#define MSR_LT_CONTROL 0x2e7 +#define LT_CONTROL_LOCK_BIT (0) #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define SMM_FEATURE_CONTROL_MSR 0x4e0 |