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authorShelley Chen <shchen@chromium.org>2018-01-31 15:55:50 -0800
committerShelley Chen <shchen@google.com>2018-02-05 19:22:44 +0000
commit50db9a208e743ecbbadfde6643e7aeaf425eacdf (patch)
treed44550cee106f574f3e3198ec38546083c87d997 /src/soc/intel/common/block/include
parent1177bf516540b62e54cefdf346bb6e8a7c376642 (diff)
soc/intel/skylake: Set PsysPl3 and Pl4
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 45f201c7da..7aa81f09ea 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -114,6 +114,8 @@
#define PKG_POWER_LIMIT_CLAMP (1 << 16)
#define PKG_POWER_LIMIT_TIME_SHIFT 17
#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
+#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
+#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f)
/* SMM save state MSRs */
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22