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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2023-09-21 23:54:53 +0530
committerSubrata Banik <subratabanik@google.com>2023-10-04 05:48:23 +0000
commit183092743b85533bdbd2e5a706980561786dbd34 (patch)
treedde446133e8d2b9e7169fabde4263c4ee03f5cb1 /src/soc/intel/common/block/include
parent7542fa19a969dcd13a1fd23d23f91ad7898e5f65 (diff)
soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
CSE firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. In the subsequent patches, a CMOS structure to store PSR back-up status will be added. The current SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET of 68 can only store cse_specific_info, as ramtop is at offset 100 and PSR back-up status structure will not be able to fit within the range. This patch overrides the SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET to 161 to accommodate all CSE related info in adjacent CMOS memory. BUG=b:273207144 TEST=Verify CSE RW FW versions are stored in CMOS memory in rex. Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78054 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
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