diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-01 06:54:44 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-04 14:44:04 +0000 |
| commit | 0b92aa618fbb73363501b8bfb8e9f51bdd9e3b3e (patch) | |
| tree | f73dce20d1a01981d62969afc3b043ca9329d74c /src/soc/intel/common/block/include | |
| parent | de91780c3089e8a46be8ee7a196acaefa6bcf115 (diff) | |
soc/intel: Rename heci_init to cse_init
This patch renames heci_init() to cse_init() as HECI initialization
should have a bigger scope than just initializing the CSE
(a.k.a HECI1 alone).
BUG=none
TEST=Able to build and boot google/taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 8fd8ba0e1a..28bc2503be 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -326,8 +326,12 @@ struct cse_boot_perf_rsp { uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA]; } __packed; -/* set up device for use in early boot enviroument with temp bar */ -void heci_init(uintptr_t bar); +/* + * Initialize the CSE device. + * + * Set up CSE device for use in early boot environment with temp bar. + */ +void cse_init(uintptr_t bar); /* * Send message from BIOS_HOST_ADDR to cse_addr. |