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authorSubrata Banik <subrata.banik@intel.com>2017-11-27 18:23:36 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-12-07 02:38:44 +0000
commitfa7cc7823a996d7ccfae754b269412c6b807744d (patch)
tree5cd38f16f2b8e5dfad4a56e8cbab0765ecdf6686 /src/soc/intel/common/block/include/intelblocks
parent85dc0d8daedc496435bba8c4c2a740b70f97ae9c (diff)
soc/intel/common/block: Add Intel common Graphics controller support
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/graphics.h54
1 files changed, 54 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h
new file mode 100644
index 0000000000..f489e27a7b
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/graphics.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H
+#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H
+
+#include <device/device.h>
+
+/*
+ * SoC overrides
+ *
+ * All new SoC must implement below functionality.
+ */
+
+/*
+ * Perform Graphics Initialization in ramstage
+ * Input:
+ * struct device *dev: device structure
+ */
+void graphics_soc_init(struct device *dev);
+
+/*
+ * Write ASL entry for Graphics opregion
+ * Input:
+ * device_t device: device structure
+ * current: start address of graphics opregion
+ * rsdp: pointer to RSDT (and XSDT) structure
+ *
+ * Output:
+ * End address of graphics opregion so that the called
+ * can use the same for future calls to write_acpi_tables
+ */
+uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
+ uintptr_t current, struct acpi_rsdp *rsdp);
+
+/* Graphics MMIO register read/write APIs */
+uint32_t graphics_gtt_read(unsigned long reg);
+void graphics_gtt_write(unsigned long reg, uint32_t data);
+void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask);
+uintptr_t graphics_get_memory_base(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */