diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-09-12 17:18:20 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-04 09:47:29 +0000 |
| commit | f87ff33a898e93012112bf9a446182ac7e024bc8 (patch) | |
| tree | 975718ba37d19aa68afd4fb4b46cce9c9a8426a1 /src/soc/intel/common/block/include/intelblocks | |
| parent | 89ac87a976e2ace9a3637c99209adec492566d30 (diff) | |
soc/intel/common/block/cse: Add boot partition related APIs
In CSE Firmware Custom SKU, CSE region is logically divided into
2 boot partitions. These boot partitions are represented by BP1(RO),
BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either
RO(BP1) or RW(BP2).
The CSE Firmware Custom SKU layout appears as below:
------------- -------------------- ---------------------
|CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA |
------------- -------------------- ---------------------
In order to support CSE FW update to RW region, below APIs help coreboot
to get info about the boot partitions, and allows coreboot to set CSE
to boot from required boot partition (either RO(BP1) or RW(BP2)).
GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE
region. The API provides info on boot partitions like start/end offsets
of a partition within CSE region, and their version and partition status.
SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from.
With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2)
on next boot.
As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3,
so coreboot sets CSE to boot from RW(BP2) in normal mode and further,
coreboot ensure CSE to boot from whichever is selected boot partition
if system is in recovery mode.
BUG=b:145809764
TEST=Verified on hatch
Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index ead5d41e8c..5cad63c47f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -23,6 +23,7 @@ #define MKHI_GROUP_ID_CBM 0x0 #define MKHI_GROUP_ID_HMRFPO 0x5 #define MKHI_GROUP_ID_GEN 0xff +#define MKHI_GROUP_ID_BUP_COMMON 0xf0 /* Global Reset Command ID */ #define MKHI_CBM_GLOBAL_RESET_REQ 0xb @@ -37,6 +38,10 @@ /* Get Firmware Version Command Id */ #define MKHI_GEN_GET_FW_VERSION 0x2 +/* Boot partition info and set boot partition info command ids */ +#define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c +#define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d + /* ME Current Working States */ #define ME_HFS1_CWS_NORMAL 0x5 @@ -219,4 +224,13 @@ bool cse_is_hfs3_fw_sku_custom(void); * Returns 0 on failure and 1 on success. */ uint8_t cse_wait_com_soft_temp_disable(void); + +/* + * The CSE Custom SKU supports notion of RO and RW boot partitions. The function will set + * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to + * boot from RW and triggers recovery mode if CSE fails to jump to RW. + * In software triggered recovery mode, the function allows CSE to boot from whatever is + * currently selected partition. + */ +void cse_fw_sync(void *unused); #endif // SOC_INTEL_COMMON_CSE_H |