diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-02-08 01:01:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-02-12 04:13:23 +0000 |
| commit | e9fd562a833f9a5754cd2398444f519d1fd410c6 (patch) | |
| tree | 75ec3bbd32effd8190bc980fd9262d9417c97fd3 /src/soc/intel/common/block/include/intelblocks | |
| parent | a2eca49d837880dbdb8f07c7022fc740def4e4e4 (diff) | |
soc/intel/cmn/sa: Refactor SA common code
Leverages common SA header definitions for Host Bridge registers.
Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
Additionally, made some minor code alignment corrections while
adding newer macros in the header file.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/systemagent.h | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 64e9be6bf9..3d4ff25a9d 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -10,12 +10,18 @@ /* Device 0:0.0 PCI configuration space */ #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ +#define GGC 0x50 /* GMCH Graphics Control Register */ +#define G_GMS_OFFSET 0x8 +#define G_GMS_MASK 0xff00 +#define G_GGMS_OFFSET 0x6 +#define G_GGMS_MASK 0xc0 +#define DPR 0x5C /* DMA Protected Range Register */ +#define PCIEXBAR 0x60 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ /* PCIEXBAR register fields */ #define PCIEXBAR_LENGTH_4096MB 6 @@ -27,13 +33,6 @@ #define PCIEXBAR_LENGTH_256MB 0 #define PCIEXBAR_PCIEXBAREN (1 << 0) -/* GMCH Graphics Control Register */ -#define GGC 0x50 -#define G_GMS_OFFSET 0x8 -#define G_GMS_MASK 0xff00 -#define G_GGMS_OFFSET 0x6 -#define G_GGMS_MASK 0xc0 - /* MCHBAR */ #define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) |