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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-07-26 16:18:43 -0600
committerKarthik Ramasubramanian <kramasub@google.com>2021-07-28 16:13:06 +0000
commitce227fe02d9695993e33403cd5eb3537c7bfff92 (patch)
tree0021fb03336e422ab2d973545c6fe8c8bbd4bdfe /src/soc/intel/common/block/include/intelblocks
parent2e17d7b89406c89217cfc0966b55b8a211ff8298 (diff)
Revert "soc/intel/common/block/gpio: Add support to program VCCIO selection"
This reverts commit 4c569b52f6053fc39cb07eed4a0753ade567c5b6. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. BUG=None TEST=Build and boot to OS in Storo. Ensure that the regressed peripherals are working back again. Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio_defs.h16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index 212a0c745b..d3249bcbbb 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -123,14 +123,6 @@
#define PAD_CFG1_TOL_1V8 (0x1 << 25)
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
-/* On SoCs with more than 2 PAD_CFG registers, some of them support programmable VCCIO.
- 0(default)=3.3V, 1=1.8V */
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL)
-#define PAD_CFG2_VCCIOSEL_MASK (0x1 << 8)
-#define PAD_CFG2_VCCIOSEL_3V3 (0x0 << 8)
-#define PAD_CFG2_VCCIOSEL_1V8 (0x1 << 8)
-#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL */
-
#define PAD_FUNC(value) PAD_CFG0_MODE_##value
#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
#define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value
@@ -260,14 +252,6 @@
PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
-/* General purpose output with VCCIO Select. */
-#define PAD_CFG_GPO_VCCIOSEL(pad, val, rst, vcciosel) \
- _PAD_CFG_STRUCT_3(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | \
- PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
- PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \
- PAD_CFG2_VCCIOSEL_##vcciosel)
-
/* General purpose input */
#define PAD_CFG_GPI(pad, pull, rst) \
_PAD_CFG_STRUCT(pad, \