diff options
| author | Anil Kumar <anil.kumar.k@intel.corp-partner.google.com> | 2023-04-18 11:03:34 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-04 05:50:56 +0000 |
| commit | 7b2edc3b6b5ecd37112d5e07f4601b68b2aea038 (patch) | |
| tree | 6098aa9178929601cf78e8171b3ea15c17357762 /src/soc/intel/common/block/include/intelblocks | |
| parent | 98fb5ffd6b934edd5be7c9ac753d2763dfbafba9 (diff) | |
soc/intel/cse: Back up PSR data during CSE FW downgrade
During CSE FW downgrade we erase CSE data. This would result in
Platform Service Record(PSR) data also to be erased.
To avoid losing PSR data we need to make a backup before data clear.
This patch sends PSR_HECI_FW_DOWNGRADE_BACKUP HECI command to CSE,
informing the CSE to backup PSR data before a data clear operation
during downgrade.
CMOS memory is used to track the backup status. PENDING is the default
state, it is updated to DONE once PSR_HECI_FW_DOWNGRADE_BACKUP HECI
command is sent.
PSR data can be backed up only post DRAM is initialized. The idea is to
perform cse_fw_sync actions in ramstage when PSR is enabled on a
platform. As part of the cse_fw_sync actions, when a firmware downgrade
is requested the command to back-up data is sent. Once the backup has
been done, trigger the firmware downgrade.
BRANCH=None
BUG=b:273207144
TEST=build CB image for google/rex board and check PSR backup command
is being sent during a CSE FW downgrade. Also check PSR data is not
lost/erased after a downgrade using intel PSR tool.
Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index ebf20ed857..b177e1364f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -80,6 +80,9 @@ enum me_fw_sku { /* Number of cse boot performance data */ #define NUM_CSE_BOOT_PERF_DATA 64 +/* PSR_HECI_FW_DOWNGRADE_BACKUP Command */ +#define PSR_HECI_FW_DOWNGRADE_BACKUP 0x3 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40, @@ -105,6 +108,24 @@ struct mkhi_hdr { uint8_t result; } __packed; +/* PSR HECI message status */ +enum psr_status { + PSR_STATUS_SUCCESS, + PSR_STATUS_FEATURE_NOT_SUPPORTED, + PSR_STATUS_UPID_DISABLED, + PSR_STATUS_ACTION_NOT_ALLOWED, + PSR_STATUS_INVALID_INPUT_PARAMETER, + PSR_STATUS_INTERNAL_ERROR, + PSR_STATUS_NOT_ALLOWED_AFTER_EOP, +}; + +/* PSR HECI message header */ +struct psr_heci_header { + uint8_t command; + uint8_t reserved; + uint16_t length; +} __packed; + /* CSE FW Version */ struct fw_version { uint16_t major; @@ -398,6 +419,9 @@ int cse_hmrfpo_get_status(void); /* Fixed Address MEI Header's ME Address field value */ #define HECI_MKHI_ADDR 0x07 +/* Fixed Address MEI Header's ME Address field value for PSR messages */ +#define HECI_PSR_ADDR 0x04 + /* Fixed Address MEI Header's ME Address for MEI bus messages */ #define HECI_MEI_ADDR 0x00 |