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authorSubrata Banik <subrata.banik@intel.com>2019-04-10 12:19:27 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-04-13 03:25:46 +0000
commit6d569163ab680ca436b16c040e6840e969df6c61 (patch)
tree677711347a1daa7aad787b0f57b1a2deacb5ae1f /src/soc/intel/common/block/include/intelblocks
parent459df6697a150e0be5dd0378d98ef54eff520641 (diff)
soc/intel/cpulib: Remove redundent enable/disable functions
This patch removes multiple enable/disable function definitions and make use of single function with argument to know feature status (enable/disable). Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h22
1 files changed, 8 insertions, 14 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 5cea96e409..70ad253607 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -97,24 +97,18 @@ enum {
int cpu_get_burst_mode_state(void);
/*
- * Enable Burst mode.
+ * Program CPU Burst mode
+ * true = Enable Burst mode.
+ * false = Disable Burst mode.
*/
-void cpu_enable_burst_mode(void);
+void cpu_burst_mode(bool burst_mode_status);
/*
- * Disable Burst mode.
+ * Program Enhanced Intel Speed Step Technology
+ * true = Enable EIST.
+ * false = Disable EIST.
*/
-void cpu_disable_burst_mode(void);
-
-/*
- * Enable Intel Enhanced Speed Step Technology.
- */
-void cpu_enable_eist(void);
-
-/*
- * Disable Intel Enhanced Speed Step Technology.
- */
-void cpu_disable_eist(void);
+void cpu_set_eist(bool eist_status);
/*
* Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120