soc/intel/{adl, common}: provide a list of D-states to enter LPM

This was done previously for ADL. moving the code to common so
it can be leveraged for other platforms (e.g. MTL)

TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

1 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index b03f6ccb2b..c149c6939e 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -127,4 +127,31 @@ enum core_type get_soc_cpu_type(void);
 
 /* Check if CPU supports Nominal frequency or not */
 bool soc_is_nominal_freq_supported(void);
+
+/* Min sleep state per device*/
+struct min_sleep_state {
+	uint8_t pci_dev;
+	enum acpi_device_sleep_states min_sleep_state;
+};
+
+/*
+ * This SOC callback returns an array that maps devices to their min sleep state.
+ * Example:
+ *
+ * static struct min_sleep_state min_pci_sleep_states[] = {
+ *	{ SA_DEVFN_ROOT,	ACPI_DEVICE_SLEEP_D3 },
+ *	{ SA_DEVFN_CPU_PCIE1_0,	ACPI_DEVICE_SLEEP_D3 },
+ *	{ SA_DEVFN_IGD,		ACPI_DEVICE_SLEEP_D3 },
+ *	...
+ * };
+ *
+ * const struct pad_config *variant_early_gpio_table(size_t *num)
+ * {
+ *	*num = ARRAY_SIZE(early_gpio_table);
+ *	return early_gpio_table;
+ * }
+ *
+ */
+struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size);
+
 #endif				/* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */