soc/intel/*: drop UART pad configuration from common code

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.

Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.

Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao

1 files changed, 1 insertions, 12 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
index c3a22bc96b..f140fc87fd 100644
--- a/src/soc/intel/common/block/include/intelblocks/uart.h
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -5,24 +5,13 @@
 
 #include <console/uart.h>
 #include <device/device.h>
-#include <intelblocks/gpio.h>
 #include <stdint.h>
 
-#define MAX_GPIO_PAD_PER_UART		2
-
-struct uart_controller_config {
-	int console_index;
-	/* devfn in PCI_DEVFN() format */
-	unsigned int devfn;
-	struct pad_config gpios[MAX_GPIO_PAD_PER_UART];
-};
-
 /*
  * While using this common UART block for any SOC following is expected from soc
  * 1. SOC will define proper UART_BASE which is base address for UART console.
  * 2. SOC will return correct device pointer based on console index
- * 3. SOC will provide appropriate GPIO pad configuration for UART console
- * 4. SOC will allow common code to set UART into legacy mode if supported.
+ * 3. SOC will allow common code to set UART into legacy mode if supported.
  */
 
 /*