diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-11-19 13:49:21 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-11-20 17:49:00 +0000 |
| commit | 2ee30add352c56fbf5a49ed27705318adaff7893 (patch) | |
| tree | a4165c2b3e43ed371e58df8b9809c5cb141b07de /src/soc/intel/common/block/include/intelblocks | |
| parent | d7375b3fdd1b39ed029aa2a4c013e46811291469 (diff) | |
soc/intel/common/thermal: Allow thermal configuration over PMC
Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.
This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59209
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/thermal.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index 377b2f94dc..aa3318c7c4 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -3,6 +3,33 @@ #ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ #define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ +/* Catastrophic Trip Point Enable */ +#define PMC_PWRM_THERMAL_CTEN 0x150c +/* Policy Lock-Down Bit */ +#define PMC_PWRM_THERMAL_CTEN_CTENLOCK (1 << 31) +/* Catastrophic Power-Down Enable */ +#define PMC_PWRM_THERMAL_CTEN_CPDEN (1 << 0) +/* EC Thermal Sensor Reporting Enable */ +#define PMC_PWRM_THERMAL_ECRPTEN 0x1510 +/* Lock-Down Bit */ +#define PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK (1 << 31) +/* Enable PMC to EC Temp Reporting */ +#define PMC_PWRM_THERMAL_ECRPTEN_EN_RPT (1 << 0) +/* Throttle Levels */ +#define PMC_PWRM_THERMAL_TL 0x1520 +/* TL LOCK */ +#define PMC_PWRM_THERMAL_TL_TLLOCK (1 << 31) +/* TT Enable */ +#define PMC_PWRM_THERMAL_TL_TTEN (1 << 29) +/* Throttle Levels Enable */ +#define PMC_PWRM_THERMAL_TLEN 0x1528 +/* TLENLOCK */ +#define PMC_PWRM_THERMAL_TLEN_TLENLOCK (1 << 31) +/* PCH Hot Level Control */ +#define PMC_PWRM_THERMAL_PHLC 0x1540 +/* PHL Lock */ +#define PMC_PWRM_THERMAL_PHLC_PHLCLOCK (1 << 31) + /* Enable thermal sensor power management */ void pch_thermal_configuration(void); |