diff options
author | Furquan Shaikh <furquan@google.com> | 2021-01-12 16:09:43 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:27:43 +0000 |
commit | ea3e6b06cc82a64d16616399362d373bfcef8a60 (patch) | |
tree | f9c15dd02ba417fe448ac4ba9b6535936176816c /src/soc/intel/common/block/include/intelblocks/pcie_rp.h | |
parent | 7cc513557d41ea86e4c5ce4a9dba14b879c8b7b2 (diff) |
soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous
In case of CPU PCIe RPs, the RP numbers might not be contiguous for
all the functions in a slot.
Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as
per the FSP expectations.
Hence, this change updates the defintion of `struct pcie_rp_group` to
include a `start` member which indicates the starting PCI function
number within the group. All common functions for PCIe RP are
accordingly updated to take the `start` member into account.
Thus, in the above example, ADL can provide a cpu_rp_table as follows:
{
{ .slot = PCIE_SLOT_6, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_1, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_6, .start = 2, .count = 1 },
}
Since start defaults to 0 when uninitialized, current PCH RP group
tables don't need to be updated.
Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/pcie_rp.h')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 264c43f585..578a600e5b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -10,15 +10,27 @@ * functions. * * `slot` is the PCI device/slot number of such a group. - * `count` is the number of functions within the group. It is assumed that - * the first group includes the RPs 1 to the first group's `count` and that - * adjacent groups follow without gaps in the numbering. + * `start` is the initial PCI function number within the group. This is useful in case the + * root port numbers are not contiguous within the slot. + * `count` is the number of functions within the group starting with the `start` function + * number. */ struct pcie_rp_group { unsigned int slot; + unsigned int start; unsigned int count; }; +static inline unsigned int rp_start_fn(const struct pcie_rp_group *group) +{ + return group->start; +} + +static inline unsigned int rp_end_fn(const struct pcie_rp_group *group) +{ + return group->start + group->count - 1; +} + /* * Update PCI paths of the root ports in the devicetree. * @@ -32,7 +44,9 @@ struct pcie_rp_group { * Call this once, after root ports have been reordered, but before PCI * enumeration. * - * `groups` points to a list of groups terminated by an entry with `count == 0`. + * `groups` points to a list of groups terminated by an entry with `count == 0`. It is assumed + * that the first group includes the RPs 1 to the first group's `count` and that adjacent groups + * follow without gaps in the numbering. */ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); |