diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-07-22 00:48:37 -0600 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:30:48 +0000 |
| commit | 4c569b52f6053fc39cb07eed4a0753ade567c5b6 (patch) | |
| tree | a7a346600b747651c9af5f0bb53a23fa6ff63b3f /src/soc/intel/common/block/gpio | |
| parent | 9b6a3a0370ef310c36d5457e8cb0bb752a8418e8 (diff) | |
soc/intel/common/block/gpio: Add support to program VCCIO selection
Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/gpio')
| -rw-r--r-- | src/soc/intel/common/block/gpio/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index c946545355..1c76c0a319 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -36,4 +36,9 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT bool default n +# Used to program VCCIO Selection as 1.8V or 3.3V +config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL + bool + default n + endif diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d4a312bf9a..5591805120 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -39,7 +39,11 @@ PAD_CFG1_IOSSTATE_MASK) #endif +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL) +#define PAD_DW2_MASK (PAD_CFG2_VCCIOSEL_MASK | PAD_CFG2_DEBOUNCE_MASK) +#else #define PAD_DW2_MASK (PAD_CFG2_DEBOUNCE_MASK) +#endif /* SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL */ #define PAD_DW3_MASK (0) #define MISCCFG_GPE0_DW0_SHIFT 8 |