soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver

The fast SPI controller (usually handling the boot NOR flash) is a
different controller type than the generic SPI controllers as it
provides access to the boot flash and usually is not used for generic
SPI slave connections.

Though there is common code for the fast SPI controller it currently do
not uses the PCI driver structure. This patch adds the PCI driver
envelope to the fast SPI driver and moves Apollo Lake as the first
platform to this driver.

Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 19 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 63fb68c2f7..9788493e1e 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -5,7 +5,9 @@
 #include <arch/romstage.h>
 #include <device/mmio.h>
 #include <assert.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
@@ -453,3 +455,20 @@ void fast_spi_clear_outstanding_status(void)
 	/* Make sure all W1C status bits get cleared. */
 	write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
 }
+
+static struct device_operations fast_spi_dev_ops = {
+	.read_resources			= pci_dev_read_resources,
+	.set_resources			= pci_dev_set_resources,
+	.enable_resources		= pci_dev_enable_resources,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_APL_HWSEQ_SPI,
+	0
+};
+
+static const struct pci_driver fast_spi __pci_driver = {
+	.ops				= &fast_spi_dev_ops,
+	.vendor				= PCI_VID_INTEL,
+	.devices			= pci_device_ids,
+};