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authorWerner Zeh <werner.zeh@siemens.com>2022-08-29 12:44:02 +0200
committerPaul Fagerburg <pfagerburg@chromium.org>2022-09-22 15:34:24 +0000
commit777099046f88f96921e21ad2e0a58b2fe66b25aa (patch)
tree0169a8a4c2da1e267c49248682eaa2b3dbed85c2 /src/soc/intel/common/block/fast_spi
parent3083f359c88d1d94587b2ed715a14a3d01ca1034 (diff)
soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driver
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi')
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index ffda237d86..e46effcc4e 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -541,8 +541,23 @@ static struct device_operations fast_spi_dev_ops = {
};
static const unsigned short pci_device_ids[] = {
+ PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI,
+ PCI_DID_INTEL_ADP_P_HWSEQ_SPI,
+ PCI_DID_INTEL_ADP_S_HWSEQ_SPI,
PCI_DID_INTEL_APL_HWSEQ_SPI,
PCI_DID_INTEL_GLK_HWSEQ_SPI,
+ PCI_DID_INTEL_CMP_HWSEQ_SPI,
+ PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
+ PCI_DID_INTEL_CNL_HWSEQ_SPI,
+ PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
+ PCI_DID_INTEL_ICP_HWSEQ_SPI,
+ PCI_DID_INTEL_JSP_HWSEQ_SPI,
+ PCI_DID_INTEL_LWB_SPI,
+ PCI_DID_INTEL_LWB_SPI_SUPER,
+ PCI_DID_INTEL_MCC_SPI0,
+ PCI_DID_INTEL_MTL_HWSEQ_SPI,
+ PCI_DID_INTEL_SPR_HWSEQ_SPI,
+ PCI_DID_INTEL_TGP_SPI0,
0
};