diff options
| author | Caveh Jalali <caveh@chromium.org> | 2020-07-23 17:09:22 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-20 23:01:49 +0000 |
| commit | 9bc041187d17c711aa2355e313772b28bdb80eb8 (patch) | |
| tree | 9cef7f62868159d6516407d693ab01c8ab74f65c /src/soc/intel/common/block/cse | |
| parent | 08d5be59be4c9fc257eb72293481add0f5f76473 (diff) | |
cse_lite: Move global reset after MRC writeback
With CSE-lite enabled, we were going through the lengthy memory
training procedure twice on the first power-on boot or after full BIOS
SPI flash update. This moves the global reset performed to achieve the
CSE-lite RO to RW reboot to a later boot phase so that it happens
after the memory training data has been written to the MRC cache. Now,
the 2nd (and subsequent) reboot can utilize the memory training data
established during the 1st boot.
This reduces the first boot time by about 20s on a 16GB system.
Looking at the timing stats form cbmem, the normal boot penalty is
about 300ms - mostly attributed to running FspSiliconInit a 2nd
time. We will get this time back when the mrc_cache refactoring effort
lands (cb:44196, et. al).
BUG=b:162021048
TEST=Booted on volteer, confirmed 20s faster boot time.
Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c29b56c407..a8948be202 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -663,7 +663,11 @@ void cse_fw_sync(void *unused) } #if CONFIG(SOC_INTEL_TIGERLAKE) -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL); +/* + * This needs to happen after the MRC cache write to avoid a 2nd + * memory training sequence. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); #else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); #endif |