diff options
| author | John Zhao <john.zhao@intel.com> | 2022-01-10 10:51:24 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:20:16 +0000 |
| commit | 98ce39dce48d9f4b88fb0d71af654f4ed948ea9b (patch) | |
| tree | 782556d7c9e5c1a9698de5acfd44bda5df5cc4e3 /src/soc/intel/common/block/cse | |
| parent | 0f76a18c3a70fbdb1505a7e23b554026596be5c2 (diff) | |
soc/intel/common: Abstract the sideband access
The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/disable_heci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 664a2f7b30..1256fd1810 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -36,7 +36,7 @@ void heci_disable(void) p2sb_unhide(); /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); + status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data32, &response); if (status || response) printk(BIOS_ERR, "Fail to make CSME function disable\n"); |