diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-02-11 16:21:46 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 18:10:33 +0000 |
| commit | 148b5456715cc8eebd25878c67ce906b6fc3adce (patch) | |
| tree | 38d0d04d56bf219aef4544d6af07490a5de487d0 /src/soc/intel/common/block/cse | |
| parent | 49e669f955913c31ff526884d3973a6a7da7dca5 (diff) | |
soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c
Move cse_disable_mei_devices() from cse_eop.c into heci_disable.c,
so that platforms needing to use heci1_disable_using_pmc() can do so
without requiring cse_eop.c be unnecessarily compiled in as well.
This will allow Cannon Lake platforms to use PMC to disable HECI1 instead
of SBI, which is currently causing a hang on google/hatch (and will be
changed in a follow-on patch).
Test: build test google/{ampton,drobit,eve,akemi} boards to ensure no breakage.
Change-Id: Iee6aff570aa4465ced6ffe2968412bcbb5ff3a8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/disable_heci.c | 20 |
2 files changed, 20 insertions, 19 deletions
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index c17e2278f2..0f1d6cad2c 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -10,10 +10,6 @@ #include <timestamp.h> #include <types.h> -#define PMC_IPC_MEI_DISABLE_ID 0xa9 -#define PMC_IPC_MEI_DISABLE_SUBID_ENABLE 0 -#define PMC_IPC_MEI_DISABLE_SUBID_DISABLE 1 - enum cse_eop_result { CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED, CSE_EOP_RESULT_SUCCESS, @@ -50,21 +46,6 @@ static bool cse_disable_mei_bus(void) return true; } -bool cse_disable_mei_devices(void) -{ - struct pmc_ipc_buffer req = { 0 }; - struct pmc_ipc_buffer rsp; - uint32_t cmd; - - cmd = pmc_make_ipc_cmd(PMC_IPC_MEI_DISABLE_ID, PMC_IPC_MEI_DISABLE_SUBID_DISABLE, 0); - if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) { - printk(BIOS_ERR, "CSE: Failed to disable MEI devices\n"); - return false; - } - - return true; -} - static enum cse_eop_result cse_send_eop(void) { enum { diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index ab8b3ad934..84a09fd3b2 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -10,6 +10,7 @@ #include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmc_ipc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -17,12 +18,31 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 +#define PMC_IPC_MEI_DISABLE_ID 0xa9 +#define PMC_IPC_MEI_DISABLE_SUBID_ENABLE 0 +#define PMC_IPC_MEI_DISABLE_SUBID_DISABLE 1 + /* Disable HECI using PCR */ static void heci1_disable_using_pcr(void) { soc_disable_heci1_using_pcr(); } +bool cse_disable_mei_devices(void) +{ + struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer rsp; + uint32_t cmd; + + cmd = pmc_make_ipc_cmd(PMC_IPC_MEI_DISABLE_ID, PMC_IPC_MEI_DISABLE_SUBID_DISABLE, 0); + if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) { + printk(BIOS_ERR, "CSE: Failed to disable MEI devices\n"); + return false; + } + + return true; +} + /* Disable HECI using PMC IPC communication */ static void heci1_disable_using_pmc(void) { |