diff options
author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-10-18 20:14:07 +0530 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:44 +0000 |
commit | 361e3646357504ef8843e3f85b35a1a966b88fe1 (patch) | |
tree | 88c323733df9f243d970d98acf79c63d59e75eb7 /src/soc/intel/common/block/cse/Makefile.inc | |
parent | 0759346cd6c0dcfd300eeca216e0a2d2ed76a827 (diff) |
soc/intel/common: Move CSE RW into new FMAP region to optimize boot time
CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.
The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.
Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
--------------------------------------------------------
| Platform | Old Boot Time | New Boot Time |
--------------------------------------------------------
| JSL | 1.3s | 1.06s |
--------------------------------------------------------
| TGL | 1.63s | 1.36s |
--------------------------------------------------------
Changes:
1. Makefile change to accommodate CSE RW blob into ME_RW_A/ME_RW_B
2. Kconfig change to define CBFS name and default file name for RW blob
metadata.
3. CSE Lite Driver
BUG=b:169077783
TEST=Verified on JSL & TGL platforms
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse/Makefile.inc')
-rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 1bc69c542b..d2f94a41a9 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -7,7 +7,8 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B +regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ + $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) cbfs-files-y += $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) |