diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-03-28 17:44:20 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-03-29 07:36:18 +0000 |
| commit | b0ddae6a5bcaa5e99661a638cd6bda010f9a0477 (patch) | |
| tree | d68dbdd4403e8fdd12b8374eac149cdc5a608a3b /src/soc/intel/common/block/crashlog/crashlog.c | |
| parent | b12075876ebd89899fdae232c7e27920bdaca5df (diff) | |
soc/intel/cmn/crashlog: Add check for zero based SRAM BAR
This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.
TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.
Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/block/crashlog/crashlog.c')
| -rw-r--r-- | src/soc/intel/common/block/crashlog/crashlog.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 3bd2488846..daa5b763cf 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -301,7 +301,7 @@ void cl_get_pmc_sram_data(void) u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); u32 pmc_crashLog_size = cl_get_pmc_record_size(); - if (!cl_pmc_sram_has_mmio_access()) + if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr) return; pmc_ipc_discovery_buf_t discovery_buf = cl_get_pmc_discovery_buf(); |