diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-01 08:47:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:06:53 +0000 |
| commit | 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch) | |
| tree | 8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/soc/intel/common/block/cpu | |
| parent | 603963e1ba4147ef31a72b94304708ab416e3b6a (diff) | |
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/cpu')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 17 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/exit_car.S | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 6 |
3 files changed, 15 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 684f82786a..17b8dc063c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -17,6 +17,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> @@ -306,7 +307,7 @@ car_cqos: wrmsr /* Set CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ wrmsr @@ -339,7 +340,7 @@ car_cqos: post_code(0x27) /* Cache is populated. Use mask 1 that will block evicts */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ or $1, %edx /* select mask 1 */ @@ -410,7 +411,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $MSR_IA32_L3_MASK_1, %ecx + movl $IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -419,12 +420,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $MSR_IA32_L3_MASK_2, %ecx + mov $IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set MSR_IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -432,7 +433,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -444,11 +445,11 @@ find_llc_subleaf: cld rep stosl /* - * Set MSR_IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 86feddca43..a4d16e8022 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/cr.h> #include <intelblocks/msr.h> @@ -80,7 +81,7 @@ car_cqos_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr @@ -101,7 +102,7 @@ car_nem_enhanced_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a0496a0..ebbdabd3e8 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ void cpu_set_p_state_to_turbo_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ void cpu_set_p_state_to_nominal_tdp_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void) perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } |