diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-05 18:57:36 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-14 17:57:51 +0000 |
| commit | 13fd3c8daef57b9b7728f5145a4241f4ee15c72f (patch) | |
| tree | 9e32d9366ace75a0c8901073ef87af936d5b983b /src/soc/intel/common/block/cpu/cpulib.c | |
| parent | 91bc6d1da79b0c48d39770be84cdb2b2afde3050 (diff) | |
soc/intel/cmn/cpu: API to initialize core PRMRR
This patch implements API to sync between core
PRMRR(Processor Reserved Memory Range Registers).
Read PRMRR base and limit value from BSP and apply it on the
rest of the cores.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu/cpulib.c')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index e1bd471adf..0b91860dfd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -3,12 +3,15 @@ #include <assert.h> #include <acpi/acpigen.h> #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <arch/cpu.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> +#include <smp/node.h> #include <soc/soc_chip.h> #include <types.h> @@ -477,3 +480,24 @@ void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, if (thread) *thread = apicid & ((1 << thread_bits) - 1); } + +static void sync_core_prmrr(void) +{ + static msr_t msr_base, msr_mask; + + if (boot_cpu()) { + msr_base = rdmsr(MSR_PRMRR_BASE_0); + msr_mask = rdmsr(MSR_PRMRR_PHYS_MASK); + } else if (!intel_ht_sibling()) { + wrmsr(MSR_PRMRR_BASE_0, msr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, msr_mask); + } +} + +void init_core_prmrr(void) +{ + msr_t msr = rdmsr(MTRR_CAP_MSR); + + if (msr.lo & MTRR_CAP_PRMRR) + sync_core_prmrr(); +} |