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author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-28 14:10:37 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 06:16:53 +0000 |
commit | 087fe9fe2732db04ed62e9d49d5a84efe0656c8a (patch) | |
tree | 38e2e5c98ce54f23011e6c176018b85646fc8033 /src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | |
parent | 5a6633491158c919a5f9e0e8cf627facb3fe890e (diff) |
soc/intel/xeon_sp/bootblock.c: Report the FSP-T output
Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46885
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S')
0 files changed, 0 insertions, 0 deletions