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| author | Eren Peng <peng.eren@inventec.corp-partner.google.com> | 2024-04-25 13:25:05 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-05-12 18:51:46 +0000 |
| commit | 1a395728dfdb6a32757ba7e120eb0e62d503e447 (patch) | |
| tree | f8fab5fcc83fd08b4b007b242677fb68b3cba191 /src/soc/intel/common/acpi/pcie_clk.asl | |
| parent | a56baa1d50f7bbc7533a396b6c2e236109a14a47 (diff) | |
mb/google/brox/var/greenbayupoc: Configure board for SODIMM use
Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.
BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.
Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/common/acpi/pcie_clk.asl')
0 files changed, 0 insertions, 0 deletions