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| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-08-25 11:43:34 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2024-08-30 07:35:24 +0000 |
| commit | b571e541731af44f4bec8c9738254de577394e9c (patch) | |
| tree | 214035576f01eac234e915a4ce7b6a3c8c8c1f9b /src/soc/intel/cannonlake | |
| parent | 77ab1514607b7b379d6538729b5df04369f006c3 (diff) | |
soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"
Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.
Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions